Integrated innovative performance improvement for NoC architecture of dynamic routing in SoC

Abstract

Advancements in the area of chip fabrication led to the integration of a large number of transistors in a small space, giving rise to the multi-core processor era. Massive multicore processors facilitate innovation and research in the field of healthcare, defense, entertainment, meteorology and many others. Reduction in chip area and increment in the number of on-chip cores is accompanied by power and temperature issues. In high-performance multicore chips, power and heat are predominant constraints. High-performance massive multicore systems suffer from thermal hotspots, exacerbating the problem of reliability in deep submicron technologies. High power consumption not only increases the chip temperature but also jeopardizes the integrity of the system. Hence, there is a need to explore the holistic power and thermal optimization and management approach for massive on-chip multi-core conditions. In multi-core environments, the communication fabric performs a significant role in deciding the efficiency of the system. In multi-core processor chips, this communication foundation is predominantly a Networkon- Chip (NoC). Tradition NoC designs incorporate planar interconnects, as a result, these NoCs have long, multi-hop wireline connections for data exchange. Due to the closeness of multi-hop planar links, such NoC architectures fall prey to high latency, significant power dissipation, and temperature hotspots. Networks inspired from nature are envisioned as an enabling technology to achieve highly efficient and low power NoC designs. newline