Investigations on the implementation of low power AES counter mode architecture on FPGA for IEEE 802 16E standard

Abstract

newline Reducing the power consumption in digital circuits is a major challenge in the design of portable systems. The limited battery lifetime imposes very strict demands on the overall power dissipation of a portable system. In modern digital communication, secured data transmission is a crucial task. The data confidentiality, data integrity and authentication are the important key parameters in wireless communication. Cryptography algorithm contributes a significant amount of data confidentiality. So, number of cryptography algorithms have been developed to prevent security hacks. But, by using modern high speed advanced computational technology, most of the cryptography algorithms were hacked. In this time line, Advanced Encryption Standard (AES) is the most powerful unbreakable cryptography algorithm. newlineIn this thesis, the research is focused on the low power implementation of AES cryptography algorithm. Here, few modifications are done at the architectural level of design and the architectures are implemented using FPGA devices of Xilinx family. Four architectural models such as resource sharing loop iterative structure, component reuse and pipe line are used in AES to reduce power, delay and area. newline