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dc.coverage.spatialCertain Investigations on Hybrid Code Based Test Data Compression And Decompression Techniques with Optimum Parameters for VLSI Circuits
dc.date.accessioned2019-08-20T10:39:29Z-
dc.date.available2019-08-20T10:39:29Z-
dc.identifier.urihttp://hdl.handle.net/10603/253256-
dc.description.abstractHigher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume for testing of Intellectual property (IP) cores. Larger test data size demands higher memory requirements. Test data compression addresses this problem by reducing the test data volume without disturbing the overall system performance during testing in BIST environment. Test data compression involves adding some additional on-chip hardware before and after the scan chains. This additional hardware decompresses the test stimulus coming from the tester, it also compacts the response after the scan chains and before it goes to the tester. This permits storing the test data in a compressed form on the tester. It is also easier to newlineadopt in industry because it s compatible with the conventional design rules and test generation flows for scan testing. Test data compression provides two benefits. First, it reduces the amount of data stored on the tester, which can extend the life of older testers that have limited memory. Second, it can reduce the test time for a given test data bandwidth. Test vectors are highly compressible because typically only 1% to 5% of their bits are specified (care) bits. Test compression is an effective method for reducing test data volume and memory requirements with relatively small cost. Code based scheme is one of the suitable test data compression technique to encode the test cubes. The techniques partition the original data into symbols, and then each symbol is replaced with a code word to form the compressed data. The decompression is performed by reversing the process using a decoder that simply converts each code word into the corresponding symbol. newline newline
dc.format.extentxxvi, 187p.
dc.languageEnglish
dc.relationp.178-186
dc.rightsuniversity
dc.titleCertain investigations on hybrid code based test data compression and decompression techniques with optimum parameters for vlsi circuits
dc.title.alternative
dc.creator.researcherKalamani C
dc.subject.keywordData Compression
dc.subject.keywordDecompression
dc.subject.keywordEngineering and Technology,Engineering,Engineering Electrical and Electronic
dc.subject.keywordHybrid Code
dc.subject.keywordVLSI Circuits
dc.description.note
dc.contributor.guideParamasivam K
dc.publisher.placeChennai
dc.publisher.universityAnna University
dc.publisher.institutionFaculty of Information and Communication Engineering
dc.date.registeredn.d.
dc.date.completed2018
dc.date.awarded30/04/2018
dc.format.dimensions21 cm
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
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01_title.pdfAttached File17.69 kBAdobe PDFView/Open
02_certificates.pdf895.78 kBAdobe PDFView/Open
03_abstract.pdf193.8 kBAdobe PDFView/Open
04_acknowledgement.pdf99.67 kBAdobe PDFView/Open
05_table of contents.pdf3.68 MBAdobe PDFView/Open
06_list_of_tables.pdf3.68 MBAdobe PDFView/Open
07_list_of_figures.pdf3.68 MBAdobe PDFView/Open
08_list_of_symbols and abbreviations.pdf179.5 kBAdobe PDFView/Open
09_chapter1.pdf1.19 MBAdobe PDFView/Open
10_chapter2.pdf252.16 kBAdobe PDFView/Open
11_chapter3.pdf324.19 kBAdobe PDFView/Open
12_chapter4.pdf1.04 MBAdobe PDFView/Open
13_chapter5.pdf711.89 kBAdobe PDFView/Open
14_chapter6.pdf807.68 kBAdobe PDFView/Open
15_conclusion.pdf165.61 kBAdobe PDFView/Open
16_references.pdf189.97 kBAdobe PDFView/Open
17_list_of_publications.pdf152.32 kBAdobe PDFView/Open


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