Certain investigations on hybrid code based test data compression and decompression techniques with optimum parameters for vlsi circuits

Abstract

Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume for testing of Intellectual property (IP) cores. Larger test data size demands higher memory requirements. Test data compression addresses this problem by reducing the test data volume without disturbing the overall system performance during testing in BIST environment. Test data compression involves adding some additional on-chip hardware before and after the scan chains. This additional hardware decompresses the test stimulus coming from the tester, it also compacts the response after the scan chains and before it goes to the tester. This permits storing the test data in a compressed form on the tester. It is also easier to newlineadopt in industry because it s compatible with the conventional design rules and test generation flows for scan testing. Test data compression provides two benefits. First, it reduces the amount of data stored on the tester, which can extend the life of older testers that have limited memory. Second, it can reduce the test time for a given test data bandwidth. Test vectors are highly compressible because typically only 1% to 5% of their bits are specified (care) bits. Test compression is an effective method for reducing test data volume and memory requirements with relatively small cost. Code based scheme is one of the suitable test data compression technique to encode the test cubes. The techniques partition the original data into symbols, and then each symbol is replaced with a code word to form the compressed data. The decompression is performed by reversing the process using a decoder that simply converts each code word into the corresponding symbol. newline newline