High performance adders and on chip memory VLSI architectures for image processing applications

Abstract

Today s technology revolution in portable electronic devices requires large amounts of data processing power, area and time to realize various image processing applications. Recently, approximate data computation has proven to be a possible option for image processing applications. Achieving high accuracy or meeting a variable accuracy requirement up to 100% has become a key design objective in high quantity digital data computing applications at a real time. Therefore, high performance Very Large Scale Integration (VLSI) architectures are extensively essential in the digital signal processor design. Recent developments in the processor design also focus on the utilization of high performance adder and on-chip memory architectures. The stability and reliability are the important criteria of the design structure, which lead to reduce worst case error and to employ in a hybrid application at a real time. The constraints involved with high performance are Counterbalance ed to provide high accuracy, high speed, low power, and area efficiency. The performance of the processor core is arisen, which depend on the configuration, design parameters and effective utilization of the data path and on-chip memory architectures. Hence, in this research, high performance adders and on-chip memory architecture have been proposed to meet the design and quality requirements for image processing applications. The elementary and high utilization structure of the data path unit is in turn are the combination of the adders. newline