Development of efficient reconfigurable multipliers

Abstract

Recent technological developments in the field of signal processing have led to the wide usage of arithmetic units. Among them, the adders and multipliers are the most frequently used arithmetic blocks which occupy considerable space in any design. The results required from these blocks change based on the application. It is also seen that not all applications require accurate output from the arithmetic modules for their further newlineprocessing. Compared to an adder, the area and complexity involved in multipliers are more. This thesis focuses on the effective use of the multiplier by introducing the concept of reconfigurability into it. By incorporating reconfigurability, the same n bit multiplier architecture can produce multiple outputs with different bit width based on the requirement. Different types of multipliers are implemented for producing variable precision outputs. Additional modules are included to these reconfigurable multipliers further to improve the performance metrics like area, delay and power. A truncated multiplier based on Baugh -Wooley algorithm is made flexible to produce full width output or fixed width output based on the selection. This multiplier uses column suppression technique. The efficiency of the multiplier is further improved by introducing an error tolerant adder along with the regular adder. newline newline