Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/253189
Title: Low power architectures for discrete cosine transform
Researcher: Jessintha D
Guide(s): Kannan M
Keywords: Discrete Cosine Transform
Engineering and Technology,Engineering,Engineering Electrical and Electronic
Low Power Architectures
Power Architectures
University: Anna University
Completed Date: 2018
Abstract: Recently there has been a considerable interest in the low power implementation of Discrete Cosine Transform (DCT). This is mainly due to the fact, that DCT being the computational bottleneck of Standards such as Joint Photographic Experts Group (JPEG) and Modified Discrete Cosine Transform (MPEG). A major limitation is the operating time provided by the battery, which in turn is dependent on the characteristics of the battery and power requirement of the system. Another concern that applies to both Portable and the non-Portable system is heat dissipation. Overheating can reduce throughput and life of the battery. To address the reasons mentioned above, low power design techniques and methodologies are to be adopted in DCT architecture for image processing by Very Large Scale Integration (VLSI) System designers. DCT computation involves huge computation and so the architecture requires larger area which leads to more power dissipation. Many newlineworks have been carried out to minimize the multiplication operator in its computation because it consumes more power and area as compared to additions. To avoid multiplication operation, few approaches were framed such as Coordinate Rotation Digital Computer (CORDIC), Shift-add, Distributive arithmetic (DA), NEw Distributive arithmetic (NEDA) etc. Most of the works had given enormous power reduction at the cost of speed and image quality. In the years of 2000, VLSI circuits have been developed with scaling. For high performance, few fixed-width multiplier based DCT architectures were constructed with error compensation circuits. Accuracy and speed were improved with an optimal reduction in power. Vi Scenarios depict that works are to be carried out for DCT architecture to reduce the computations without degrading the image quality. A major classification is made after reviewing the literature as multiplier-less and multiplier based DCT. Therefore two categories of DCT architectures are designed and implemented in this research. newline newline
Pagination: xx, 138p.
URI: http://hdl.handle.net/10603/253189
Appears in Departments:Faculty of Information and Communication Engineering

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02_certificates.pdf2.34 MBAdobe PDFView/Open
03_abstract.pdf106.44 kBAdobe PDFView/Open
04_acknowledgement.pdf181.72 kBAdobe PDFView/Open
05_contents.pdf91.64 kBAdobe PDFView/Open
06_list_of_tables.pdf85.5 kBAdobe PDFView/Open
07_list_of_figures.pdf174.49 kBAdobe PDFView/Open
08_list_of_abbreviations.pdf130.21 kBAdobe PDFView/Open
09_chapter1.pdf808.36 kBAdobe PDFView/Open
10_chapter2.pdf561.98 kBAdobe PDFView/Open
11_chapter3.pdf1.33 MBAdobe PDFView/Open
12_chapter4.pdf1.34 MBAdobe PDFView/Open
13_chapter5.pdf1.17 MBAdobe PDFView/Open
14_conclusion.pdf662.35 kBAdobe PDFView/Open
15_references.pdf489.76 kBAdobe PDFView/Open
16_list_of_publications.pdf350.32 kBAdobe PDFView/Open
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