Certain analysis on efficient and reliable hybrid routing in network on chip for 3d configuration

Abstract

The main objective of this research is to develop an efficient and newlinereliable routing in Network On Chip(NOC) for 3-Dimensional(3D) newlineConfiguration. The techniques of hybrid routing are preferred due to its newlineflexibility to transfer the data in all the direction in NOC topology. The newlinerouters are implemented in 2-Dimensional(2D) configuration using hybrid newlinemethod. There is a scope for developing a router for 3D configurations. The newlineadvantage and the scope of 3D router over 2D router gives the opportunity to newlinedevelop a router model which is suitable to communicate in the multilevel newlinetopology effectively. When the number of the nodes are increased newlineprogressively, 2D Router configuration has the limitations and it travels the newlinehectic distance to reach the destination port. In this research work, Router is newlinedesigned and implemented considering the two levels of approach like newlineArchitectural level of router in Physical design and on-chip communication newlinelevel in 3D NOC environment.In architectural level, three types of 3D hybrid NOC(HYNOC) newlinerouters are designed, simulated and synthesized using Hardware Description newlineLanguage(HDL) and Field Programmable Gate Array(FPGA) device to newlineanalyse the performance of proposed design. They are 3D HYNOC router, newline3D reliable HYNOC router and 3D optimized reliable HYNOC router newline newline