Study on dynamic power optimized fpga based multiplier for image analysis

Abstract

In todayand#8223;s microelectronics scenario, there is an essential need to newlinefocus on optimized power consumption, less occupied area and minimum newlinepropagation delay in the field of Very Large Scale Integration (VLSI), which newlinemakes use of the internal system design with Field Programmable Gate Array newline(FPGA) architectures. In order to optimize the power consumption, adaptation newlineof efficient architectures and minimization of the number of instruction newlineexecutions in each sub-block is essential in a real time application system. newlineUltimately, this will reduce the total number of clock cycle executions for an newlineapplication circuit. Hence, in this research work, architectural design newlinemodifications of an image analyzer embedded inside the FPGA architecture newlineare investigated to improve efficiency with the use of dynamic power newlineoptimized FPGA based multiplier. The objective of this thesis is to obtain the newlinedynamic power optimization in the FPGA architectures, both in multiplier and newlinein the image analyzer utilizing this multiplier. In order to incorporate suitable optimized dynamic power consuming multiplier architecture inside, various multiplier architectures are newlineconsidered in this study. As the initial attempt a modified Universal Shift newlineRegister (USR) based low power shift-add multiplier is designed. newline newline