Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/252995
Title: | Development of efficient aging aware reliable multipliers for the application of error detection and correction in FIR filter |
Researcher: | Kamatchi S |
Guide(s): | Vivekanandan C |
Keywords: | Aging-Aware Engineering and Technology,Engineering,Engineering Electrical and Electronic FIR Filter Reliable Multipliers |
University: | Anna University |
Completed Date: | 2018 |
Abstract: | In VLSI system design, reducing both the power consumption and delay to execute a code have gained considerable attention from engineers and researchers in the recent past. In this aspect it is observed that the multipliers in DSP tend to consume most of the power and hence, the design of power efficient multipliers are vital in low power DSP applications. Also it is evident that if the multipliers are too slow, the performance of entire circuits will be at stake. In existing systems implemented with an aging-aware multiplier design with a Adaptive Hold Logic (AHL) circuit. The multiplier is based on the variable-latency technique and can adjust the AHL circuit to achieve reliable operation under the influence of Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) effects. The multiplier is able to provide higher throughput through the variable latency. A positively biased nMOS transistor results in PTBI effect which in turn reduces the speed of operation of the transistor and increases delay of operation due to system breakdown. In this work, an aging-aware multiplier design with novel AHL circuit is proposed with the use of Booth multiplier. Based on the input pattern, AHL circuit determines the number of cycles, one or two through judging block and this process reduces the execution time. The multiplier is based on the Booth technique with lesser switching activity and can adjust the AHL circuit to achieve reliable operation under the influence of NBTI and PBTI effects. Power optimization is achieved in traditional circuits by selecting critical path as an execution cycle period, whereas in the proposed work Razor flip-flops are used to complete the execution in one cycle, thus effectively reducing the execution time. In case of failure to accomplish the newlineexec ution in one cycle the proposed system will take additional cycle. newline newline |
Pagination: | xxi, 122p. |
URI: | http://hdl.handle.net/10603/252995 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 18.66 kB | Adobe PDF | View/Open |
02_certificates.pdf | 1.07 MB | Adobe PDF | View/Open | |
03_abstract.pdf | 175.67 kB | Adobe PDF | View/Open | |
04_acknowledgement.pdf | 92.72 kB | Adobe PDF | View/Open | |
05_contents.pdf | 15.11 MB | Adobe PDF | View/Open | |
06_list_of_symbols and abbreviations.pdf | 958.42 kB | Adobe PDF | View/Open | |
07_chapter1.pdf | 2.86 MB | Adobe PDF | View/Open | |
08_chapter2.pdf | 2.31 MB | Adobe PDF | View/Open | |
09_chapter3.pdf | 2.59 MB | Adobe PDF | View/Open | |
10_chapter4.pdf | 2.35 MB | Adobe PDF | View/Open | |
11_chapter5.pdf | 2.12 MB | Adobe PDF | View/Open | |
12_chapter6.pdf | 5.39 MB | Adobe PDF | View/Open | |
13_conclusion.pdf | 361.51 kB | Adobe PDF | View/Open | |
14_references.pdf | 1.02 MB | Adobe PDF | View/Open | |
15_list_of_publications.pdf | 229.26 kB | Adobe PDF | View/Open |
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