Design and performance analysis of novel codecs for crosstalk avoidance in parallel data communication of network on chip links

Abstract

The development of Very Large Scale Integration (VLSI) technology helps the designer to interconnect many Processing Elements in a single chip and allow the IC designers to perform faster and larger designs with added complexity. In order to achieve these complex designs, System on newlineChip (SoC) and Chip level Multiprocessing (CMP) based products are commercially available. The SoC is an architecture in which a Processing Element or many Processing Elements along with memory and also a set of peripherals have been connected by buses are integrated on a single chip. Although, the modern technology permits many Intellectual Property (IP) newlinecores to be located on a single chip and corresponding grow in Multiprocessor newlineSystem on Chip (MPSoC) architecture demands low latency, high throughput newlineand more reliability in communication services. In latest processor, the device newlineparameter variations further complicate the timing and reliability issues. newlineThe communication architecture between the Processing Elements (PE) is a big challenge for the IC designers. In System on chip, shared bus communication architecture is used to connect the Processing Elements. The newlinetraditional bus based communication architecture restricts the performance of newlinethe system needed in many applications. To handle the challenges in newlineinterconnect architecture of the SoC, the Network on Chip (NoC) has been newlineproposed. NoC is a packet based, on chip communication network consists of newlinelinks, routers and Network Interfaces (NIs). NoC offers better performance, newlinescalability and modularity for recent MPSoC architectures and reduces the communication complexity in designs newline newline