Certain Investigations on Fpga Based Design Approach for Elliptic Curve Cryptosystem

Abstract

ABSTRACT newlineToday s world sees a rapid development in the area of electronic communication systems. The advancement in information technology has reached the public to lead an easier life by choosing suitable applications from a mobile operating system. This has led to the use of pervasive devices became much popular in recent time. In fact, many of the pervasive applications use wireless communication as it is flexible with increased mobility. Since all such wireless systems are more susceptible to eavesdrop, the risk for information security is a major concern. To ensure the security of information against unauthorized access as well as manipulation, Cryptographic techniques are employed. newlineElliptic Curve Cryptography (ECC) provides a secured message communication among the pervasive devices with shorter key length. The point multiplication is a crucial operation on the Elliptic curve cryptography, which is expensive in terms of computing time, power consumption as well as area utilization. In the projective coordinate, time consuming operations are reduced. In this work various methods were scrutinized to upgrade the efficiency of Elliptic Curve Cryptography by means of finding suitable point multiplication schemes for the cryptosystem. The results obtained were analyzed for efficiency of the system by applying Karatsuba Multiplication and Lopez and Dahab point multiplication in the Galois field. The proposed ECC architecture over GF(2160) is designed with three different types of multiplication schemes using array multipliers, modified type of booth multipliers and hybrid multiplication scheme and it served as a low power multiplier. The multipliers are applied in the Montgomery scalar multiplication algorithm in order to carry out point addition and point doubling operations, in elliptic curve. This work focused in developing high performance, Elliptic Curve Cryptography architecture over the binary field. The proposed architecture justifies the suitability of design of multipliers for low power application as well