Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/24979
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dc.coverage.spatialInformation and Communication Engineeringen_US
dc.date.accessioned2014-09-12T09:16:02Z-
dc.date.available2014-09-12T09:16:02Z-
dc.date.issued2014-09-12-
dc.identifier.urihttp://hdl.handle.net/10603/24979-
dc.description.abstractClock and Data Recovery circuits have been used extensively in the receivers of optical communication systems and even today their use are expanding rapidly to a variety of applications in inter and intra chip communications Increasing speeds of operation integration and miniaturization lower operating power supply and lower power dissipation are emerging as important issues that severely limit the architectural choices newlineFurther these choices also have to operate under more and more severe constraints of power supply noise process and temperature variations The present thesis investigates the impact of power supply noise on the jitter performance of dual loop architecture of CDR circuit proposed by Seema Butala Anand et al an architecture which is considered as one of the important alternatives available for implementing CDR circuits A systematic newlinesimulation study has been carried out to determine the power supply noise sensitivity of each individual block of the dual loop CDR circuit and the quantitative results obtained are presented in this thesis Simulation results indicate that this architecture is very sensitive to power supply noise and it is demonstrated that insertion of suitable Low Dropout Regulators is essential to enhance the performance of the CDR system with respect to power supply noise newlineen_US
dc.format.extentxviii, 94p.en_US
dc.languageEnglishen_US
dc.relation-en_US
dc.rightsuniversityen_US
dc.titlePerformance studies of the dual loop clock and data recovery circuits in the presence of power supply noiseen_US
dc.title.alternative-en_US
dc.creator.researcherKhalil, Ibrahim mahmouden_US
dc.subject.keywordClock and data recoveryen_US
dc.subject.keywordData recovery circuitsen_US
dc.subject.keywordDual loop architectureen_US
dc.subject.keywordInformation and communication engineeringen_US
dc.subject.keywordLow dropout regulatorsen_US
dc.subject.keywordOptical communicationen_US
dc.subject.keywordPower supply noiseen_US
dc.description.note-en_US
dc.contributor.guideRamakrishna, P Ven_US
dc.publisher.placeChennaien_US
dc.publisher.universityAnna Universityen_US
dc.publisher.institutionFaculty of Information and Communication Engineeringen_US
dc.date.registeredn.d.en_US
dc.date.completed01/11/2010en_US
dc.date.awarded30/11/2010en_US
dc.format.dimensions23cm.en_US
dc.format.accompanyingmaterialNoneen_US
dc.source.universityUniversityen_US
dc.type.degreePh.D.en_US
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File128.33 kBAdobe PDFView/Open
02_certificates.pdf69.09 kBAdobe PDFView/Open
03_abstract.pdf7.5 kBAdobe PDFView/Open
04_acknowledgement.pdf6.42 kBAdobe PDFView/Open
05_contents.pdf26.11 kBAdobe PDFView/Open
06_chapter1.pdf22.12 kBAdobe PDFView/Open
07_chapter2.pdf484.94 kBAdobe PDFView/Open
08_chapter3.pdf290.88 kBAdobe PDFView/Open
09_chapter4.pdf9.85 kBAdobe PDFView/Open
10_chapter5.pdf514.64 kBAdobe PDFView/Open
11_references.pdf13.8 kBAdobe PDFView/Open
12_publications.pdf5.48 kBAdobe PDFView/Open
13_vitae.pdf5.34 kBAdobe PDFView/Open


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