Certain investigation on FPGA routing algorithm for reduction of power and delay

Abstract

In the concept of explosive growth in the demand of portable computing device and wireless communication systems power dissipation is becoming a growing concern. Higher power consumption reduces the battery lifetime of portable devices affects device reliability and increases cooling cost Power consumption is an important actor of designing integrated circuits Field programmable gate array FPGA is much less ower efficient when compared with cell-based Application Specific Integrated Circuits ASIC The power inefficiency has limited application of FPGA in the area newlineof low power But FPGA has advantage that it is highly adaptable and well suited for short design cycles Thus the reduction of power consumption is important in FPGA The Signal transitions are classified into two type s namely spurious transitions or glitches and functional transition Hence reducing glitches is important because the glitch power plays a major role in total dynamic power of FPGA The glitch power reduction can be done by balancing the path to inputs of look up table It causes the signals of the look up table to arrive at the same time and no glitches were generated newlineThe main problem in using Standard FPGA routing is the route time clock has constant time and will expire before receiving replies from all the neighbors when the network is denser The second issue is if the network is sparse then the route clock time will be waiting even after it receives replies from all of its neighbors The third issue in Standard FPGA routing is poor route management because the node deletes the route available once there is no data transfer for some time But when the traffic or congestion is higher in the network the response will be received after prolong time newline newline