Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/24802
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dc.coverage.spatialInformation and Communication Engineeringen_US
dc.date.accessioned2014-09-09T07:47:24Z-
dc.date.available2014-09-09T07:47:24Z-
dc.date.issued2014-09-09-
dc.identifier.urihttp://hdl.handle.net/10603/24802-
dc.description.abstractRecent oriented towards reducing the power and increasing the gain of single chip systems newlineWhile focusing the attention on low power and gain in the device the material used newlinehas to be taken into consideration newlineIn semiconductor industry emerging devices with low power and high gain newlineare mainly used in VLSI applications The primary driving factor being the increase newlinein scale of integration the chip has to accommodate smaller and faster transistors newlinethan their predecessors During the last decade conventional scaling in devices has newlinebeen a challenge for the semiconductor technology Scaling has been aimed to newlineachieve high speed low power and high density However as scaling approaches its newlinephysical limit it becomes more difficult in real time implementations Researches newlinecarried out to investigate an alternative have led to the introduction of new materials newlineand concepts to overcome the variations Highk dielectric materials are explored to newlinereduce Off current and parasitic capacitance in devices Among the different highk newlinematerials available the nano size Zirconium dioxide is suggested as the alternate newlinegate oxide material for devices due to its thermal stability and small grain boundary newlinesize based on the experiment carried out newline newlineen_US
dc.format.extentxxi,122p.en_US
dc.languageEnglishen_US
dc.relation-en_US
dc.rightsuniversityen_US
dc.titleNanoscale double gate mosfets for subthreshold low power applications using high k dielectricsen_US
dc.title.alternative-en_US
dc.creator.researcherNirmal, Den_US
dc.subject.keywordhigh k dielectricsen_US
dc.subject.keywordinformation and communication engineeringen_US
dc.subject.keywordNanoscale double gateen_US
dc.description.noteReference p.108-118 Appendix p.97-107en_US
dc.contributor.guideVijayakumar, Pen_US
dc.publisher.placeChennaien_US
dc.publisher.universityAnna Universityen_US
dc.publisher.institutionFaculty of Information and Communication Engineeringen_US
dc.date.registeredn.d.en_US
dc.date.completed01/03/2012en_US
dc.date.awarded30/03/2012en_US
dc.format.dimensions23cmen_US
dc.format.accompanyingmaterialNoneen_US
dc.source.universityUniversityen_US
dc.type.degreePh.D.en_US
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File43.67 kBAdobe PDFView/Open
02_certificates.pdf736.3 kBAdobe PDFView/Open
03_abstract.pdf14.86 kBAdobe PDFView/Open
04_acknowledgement.pdf8.06 kBAdobe PDFView/Open
05_contents.pdf44.87 kBAdobe PDFView/Open
06_chapter 1.pdf44.01 kBAdobe PDFView/Open
07_chapter 2.pdf488.87 kBAdobe PDFView/Open
08_chapter 3.pdf221.06 kBAdobe PDFView/Open
09_chapter 4.pdf1.07 MBAdobe PDFView/Open
10_chapter 5.pdf754.77 kBAdobe PDFView/Open
11_chapter 6.pdf823.44 kBAdobe PDFView/Open
12_chapter 7.pdf15.08 kBAdobe PDFView/Open
13_appendix.pdf129.52 kBAdobe PDFView/Open
14_references.pdf246.31 kBAdobe PDFView/Open
15_publications.pdf64.55 kBAdobe PDFView/Open
16_vitae.pdf7.84 kBAdobe PDFView/Open


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