Design and implementation of high Performance communication Architectures for noc system Accelerators

Abstract

International Technology Roadmap for Semiconductors ITRS newlineprojects is the latest technology moving towards a system level and platformbased newlinedesigns involving large percentage of design reuse Different newlineIntellectual Property IP cores including processor and memory are newlineinterconnected to build typical System on Chip SoC architectures Larger newlineSoC designs dictate the data communication to happen over the global newlineinterconnects At 45nm and below interconnects have profound impact on the newlineperformance due to increased delays and cross coupling from newlinemultiple sources Hence attaining minimal timing with reasonable newlineperformance and low power is increasingly becoming next to impractical newlineAlso the traditional bus based interconnection architectures present big newlinedifficulties in synchronization in the heterogeneous System on Chip newlineenvironment At system level the performance of the shared bus begins to newlinedeteriorate with increased number of cores Networks on Chip is a recent newlinesolution paradigm adopted to increase the performance o f multi core designs newline