Improvised Calibration Techniques for High Speed Pipelined ADC

Abstract

The design of high-speed and high-resolution pipelined Analog-to-Digital Convertors (ADC) is getting more and more challenging as undesirable outcomes of technology scaling, like reduced device gain and supply voltage, are making the design of precision charge transfer, using high-gain and high-speed op amps, increasingly difficult. This inaccurate charge transfer results in harmonic distortion at the output of pipelined ADCs. This thesis presents various techniques for improving the performance of pipelined ADCs.This thesis presents a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming thedrawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, opamp settling, and capacitor mismatch. Circuit level simulations in UMC 65-nm process with an an open loop op amp gain of 54 dB and capacitor mismatch of 3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB. (abstract attached). newline