Design and analysis of high Performance charge pump phase lock Loop with low current mismatch and High output impedance

Abstract

In a Phase Locked Loop PLL the Charge Pump CP circuit is newlineone of the key elements It receives Up and Down signals from the newlinePhase Frequency Detector PFD and transforms it into current signals In newlineComplementary Metal Oxide Semiconductors CMOS CPs there are two newlineswitches made up of P channel Metal Oxide Semiconductors pMOS and newlineN channel Metal Oxide Semiconductors nMOS called as Up and Down newlineswitches respectively The Drain to source voltage of pMOS and nMOS is newlinevaried depending on the phase detector output voltage thereby causing the newlinemagnitude of the currents in the pMOS IUP and nMOS IDN to differ This newlinecurrent mismatch of the CP in the PLL produces some fluctuations in a newlinevoltage controlled oscillator VCO input and therefore there is a large phase newlinenoise on the PLL output signals The prime objective of this research work is newlineto design a Charge Pump Phase Locked Loop CPPLL that can operate up to newlinea frequency of 200 MHz using Gain Boosting Charge Pump architecture newlineIt combines an error amplifier and reference current sources to achieve good newlinecurrent matching characteristics and lower phase noise At the same time the newlinecharge removal transistors is used to eliminate the charge sharing problem newline