Investigations on polar coder and paillier cryptography with efficient resource utilization

Abstract

Encoders are solitary through digital circuits organized in the entire gamut of communication schemes Discrete technologies have been designed for channel coding function This thesis presents a novel polar coding system that can attain minimization of hardware resource utilization as the polar code achieves the symmetric capacity of Binary input Discrete Memoryless Channel B DMC In particular it can asset its operations in communication sensing and information theory In this concise energetic scheme of polar encoders forth with polar decoders and paillier encryption are proposed Initially the proposed work is divided into three phases The first phase intend to construct a resource effective encoder the second phase focuses on the decoder and the third phase employs the applications of polar encoder newlinePrimitive planning focus on the existing schemes for inferring the progression of polar codes and to examine the requirement for refining the polar encoder architecture In a general scenario the most compelling challenges in Very Large Scale Integration VLSI design consist of trade off enclosed by complexity throughput and hardware utilization Efficient polar encoders audit distinct signal processing techniques such as pipelining parallelism puncturing interleaving, folding and register merging in the aspects of VLSI implementation Ultimately the constraints in the applications of polar codes are tested A study of various techniques of hardware utilization using different schemes to develop polar encoder architecture is recommended newline newline