Certain Investigation On Optimized Area And Power Delay Product In Digital Circuit Applications

Abstract

Owing to explosive growth of laptops portable personal newlinecommunication systems and the evolution of the shrinking technology the newlineresearch effort in lowpower electronics has become intensified Today the newlineincreasing number of portable applications requires smallarea lowpower newlinehigh throughput circuitry Therefore circuits with lowpower consumption newlinehave become the major design of systems Technology trends show that the newlinecircuit delay has scaled down by 30 while performance and transistor newlinedensity have doubled approximately every two years Likewise the newlinetransistors threshold voltage is reduced by almost 15 by every generation newlineAll of these technological trends have led to higher power consumption in newlinecircuits which increase chip temperature and decrease the battery life newlineThe 1bit full adder circuit is one of the most important newlinecomponents of any digital system application The powerdelay product is a newlinemeasurement of the energy expanded per operational cycle of an arithmetic newlinecircuit A low power full adder based on a new logic approach reduces the newlinepower consumption by implementing using 2to1 multiplexer with 12 newlinetransistors This circuit has no direct connections to power supply nodes and newlinethe entire signal gates are directly excited by the fresh input signals leading to newlinenoticeable reduction in short circuit power consumption The proposed MUX newlinebased adder shows a significant improvement in power delay product than newlinethat of the earlier designed adders Simulation results are performed by newlineTANNEREDA with 3V supply based on 018 m CMOS technology The newlineresults show that the proposed circuit has the lowest powerdelay product newlinewith a significant improvement in silicon area newlineFast multipliers are essential parts of digital signal processing newlinesystems The speed of multiply operation is of great important in digital signal newlineprocessing as well as in the general purpose processors today New multiplier architecture is proposed for low power and high speed application newline