Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/240479
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2019-05-01T05:51:13Z-
dc.date.available2019-05-01T05:51:13Z-
dc.identifier.urihttp://hdl.handle.net/10603/240479-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleimplementation of virtual channel in a network on chip router
dc.title.alternative
dc.creator.researcherDamala Dayakar Rao
dc.subject.keywordEngineering and Technology,Engineering,Engineering Electrical and Electronic
dc.description.note
dc.contributor.guideP.v.naganjaneyulu
dc.publisher.placeJhunjhunu
dc.publisher.universityShri Jagdishprasad Jhabarmal Tibarewala University
dc.publisher.institutionFaculty of Engineering
dc.date.registered26/06/2016
dc.date.completed03/09/2018
dc.date.awarded01/02/2019
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File65.31 kBAdobe PDFView/Open
02_declaration by candidate.pdf12.01 kBAdobe PDFView/Open
03_certificate.pdf12.15 kBAdobe PDFView/Open
04_acknowledgment.pdf5.71 kBAdobe PDFView/Open
05_contents.pdf32.71 kBAdobe PDFView/Open
06_list of tables.pdf12.43 kBAdobe PDFView/Open
07_list of figures.pdf33.23 kBAdobe PDFView/Open
08_abbreviation.pdf9.42 kBAdobe PDFView/Open
09_abstact.pdf8.2 kBAdobe PDFView/Open
10_chapter 1.pdf21.17 MBAdobe PDFView/Open
11_chapter 2.pdf205.62 kBAdobe PDFView/Open
12_chapter 3.pdf4.49 MBAdobe PDFView/Open
13_chapter 4.pdf17.42 MBAdobe PDFView/Open
14_chapter 5.pdf39.48 MBAdobe PDFView/Open
15_chapter 6.pdf79.39 kBAdobe PDFView/Open
16_bibliography.pdf26.17 kBAdobe PDFView/Open
17_appendix.pdf759.53 kBAdobe PDFView/Open


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