Certain Investigations On Power Reduction In A Viterbi Decoder Using Low Power VlSI Architectures

Abstract

Rapid developments in the field of wireless communication have newlinecreated a rising demand for Viterbi decoder with long battery life low power newlinedissipation and low weight Despite the significant progress in the last decade newlinethe problems of power dissipation in the Viterbi decoder still remains newlinechallenging and require further technical solutions Hence this research newlinefocuses on designing low power VLSI Very Large Scale Integration newlinearchitectures for the Viterbi decoder for a constraint length of K3 and newlinediscuss their performances in terms of power speed and area The newlineconvolutional encoders are designed for constraint length of K3 to7 Thus newlinethe performance of the Viterbi decoder is improved by low power VLSI newlinetechniques newlineIn order to reduce the power consumption and to increase the speed newlineof the Viterbi decoder repeated iterations are performed at the same clock newlinetransition by unfolding algorithm This unfolding algorithm is applied at the newlinebit level to generate digitserial architecture which processes multiple words newlineper clock cycle The obtained results are compared with the existing 2 bit newlinelevel pipelined look ahead technique It is observed that the proposed method newlinereduced power consumption by 2576 with 1009 increase in speed The newlinelimitation of this method is addressed by wave pipelining technique and it is newlineimplemented to increase the speed of the architecture as the idle time of the newlinenon critical paths is reduced newlineThe combined technique of Self Reset Logic SRL with wave newlinepipelining is used to design the architecture for the Viterbi decoder to reduce newlinethe power dissipation Power consumption of the wave pipelining work is newlinereduced by a factor of 7231 when compared to the existing single rail newlinedomino logic The area of the decoder increases with respect to its advantage newlineof increase in speed newlineVLSI architecture for a Viterbi decoder based on GDI Gate newlineDiffusion Input is designed to minimize the number of transistors and newlinetransitions Thus the problem of high gate density in SRL based design is newlineaddressed by the GDI approach newline newline