Development of algorithms for test generation and simulation of crosstalk delay faults in vlsi circuits

Abstract

Very Large Scale Integration VLSI is the fabrication of millions newlineof components on the same chip and is an integral part of modern electronic newlinesystems Due to the significant advances in VLSI technology new Automatic newlineTest Pattern Generation ATPG problems are emerging The move towards newlinedeep submicron technology introduces timing related defects that change the newlinetiming of the circuit instead of its function Timing related defects include newlineexternal noise sources and process variations newlineOf the various noise sources crosstalk noise will have significant newlineimpact on the performance of deep submicron systems Crosstalk can induce newlineboth logic errors and delay faults While many techniques have been proposed newlineto reduce crosstalk due to limited design margin and unpredictable process newlinevariations testing for crosstalk must be performed during manufacturing to newlineenhance device reliability and yield Hence efficient test generation newlinemethodologies for crosstalk delay faults have to be developed newline newline