Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/23594
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dc.coverage.spatialReconfigurable architecture for High performance turbo decoderen_US
dc.date.accessioned2014-08-21T05:12:56Z-
dc.date.available2014-08-21T05:12:56Z-
dc.date.issued2014-08-21-
dc.identifier.urihttp://hdl.handle.net/10603/23594-
dc.description.abstractIn digital communication error correction codes are the essential components to ensure robust digital applications Turbo code is one of the most attractive near Shannon limit error correction codes One key feature associated with turbo code is iterative decoding process It enables the turbo code to achieve the outstanding performance with moderate complexity However iterative process leads to low decoding throughput In order to achieve high decoding throughput large computation units are instantiated for each soft input soft output decoder and this results high complexity and more power consumption But nowadays in contrast the growing market of newlinewireless portable devices insists the industry to focus on compact low power circuit implementations Hence there is a need for innovations on Very Large Scale Integration design of high speed Turbo Decoders that are both area and power efficient In this work an efficient VLSI architecture for turbo decoding is proposed The proposed reconfigurable architecture for turbo decoder is based on Max Log MAP algorithm with sliding window technique Max Log MAP algorithm offers a good compromise between performance and complexity Hence it is selected for the proposed work The sliding window technique provides efficient resource usage to the proposed architecture by dividing a block of input symbols into a number of sub blocks newline newlineen_US
dc.format.extentxviii, 119p.en_US
dc.languageEnglishen_US
dc.relationp,108-117.en_US
dc.rightsuniversityen_US
dc.titleDesign of reconfigurable architecture for high performance turbo decoderen_US
dc.title.alternativeen_US
dc.creator.researcherMathana J Men_US
dc.subject.keywordDigital communication error correction codesen_US
dc.subject.keywordHigh performance turbo decoderen_US
dc.subject.keywordInformation and communication engineeringen_US
dc.subject.keywordVery Large Scale Integration designen_US
dc.description.noteReferences p.108-117,en_US
dc.contributor.guideRaja paul perinbam Jen_US
dc.publisher.placeChennaien_US
dc.publisher.universityAnna Universityen_US
dc.publisher.institutionFaculty of Information and Communication Engineeringen_US
dc.date.registerednen_US
dc.date.completed01/09/2012en_US
dc.date.awarded30/09/2013en_US
dc.format.dimensions23cm.en_US
dc.format.accompanyingmaterialNoneen_US
dc.source.universityUniversityen_US
dc.type.degreePh.D.en_US
Appears in Departments:Faculty of Information and Communication Engineering

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02_certificate.pdf654.77 kBAdobe PDFView/Open
03_abstract.pdf10.52 kBAdobe PDFView/Open
04_acknowledgement.pdf6.52 kBAdobe PDFView/Open
05_contents.pdf30.01 kBAdobe PDFView/Open
06_chapter1.pdf109.45 kBAdobe PDFView/Open
07_chapter2.pdf288.57 kBAdobe PDFView/Open
08_chapter3.pdf1.58 MBAdobe PDFView/Open
09_chapter4.pdf1.33 MBAdobe PDFView/Open
10_chapter5.pdf435.15 kBAdobe PDFView/Open
11_chapter6.pdf19.72 kBAdobe PDFView/Open
12_references.pdf46.64 kBAdobe PDFView/Open
13_publications.pdf7.25 kBAdobe PDFView/Open
14_vitae.pdf5.95 kBAdobe PDFView/Open


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