1. Shodhganga@INFLIBNET
  2. Anna University
  3. Faculty of Information and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/234098
Title: A novel flip flop based error free area efficient and low power pipeline architecture for finite impulse recursive system
Researcher: K, Raja
Guide(s): Saravanan, S
Keywords: Circuitsimulation
Clockgating
Dilation
Flip-flop
Pipeline
University: Anna University
Completed Date: 2017
Abstract: Abstract available
Pagination: xxiii, 130p.
URI: http://hdl.handle.net/10603/234098
Appears in Departments:Faculty of Information and Communication Engineering

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01_title page.pdfAttached File9.6 kBAdobe PDFView/Open
02_certificate.pdf359.1 kBAdobe PDFView/Open
03_abstract.pdf59.73 kBAdobe PDFView/Open
04_acknowledgement.pdf146.98 kBAdobe PDFView/Open
05_table of content.pdf220.19 kBAdobe PDFView/Open
06_list of table.pdf4.64 kBAdobe PDFView/Open
07_list of figures.pdf68.15 kBAdobe PDFView/Open
08_list of abbreviation.pdf14.01 kBAdobe PDFView/Open
09_chapter 1.pdf181.19 kBAdobe PDFView/Open
10_chapter 2.pdf272.68 kBAdobe PDFView/Open
11_chapter 3.pdf744.63 kBAdobe PDFView/Open
12_chapter 4.pdf819.05 kBAdobe PDFView/Open
13_chapter 5.pdf566.97 kBAdobe PDFView/Open
14_chapter 6.pdf938.25 kBAdobe PDFView/Open
15_chapter 7.pdf68.58 kBAdobe PDFView/Open
16_references.pdf541.12 kBAdobe PDFView/Open
17_list of publication.pdf59.71 kBAdobe PDFView/Open
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