Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/233476
Title: Code compression and decompression technique for MIPS32 bit processor
Researcher: G, Ramani
Guide(s): Geetha, K
Keywords: Bit
Chip
Code
Compressor
MIPS32
University: Anna University
Completed Date: 2018
Abstract: Abstract available
Pagination: xv, 123p.
URI: http://hdl.handle.net/10603/233476
Appears in Departments:Faculty of Electrical Engineering

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01_title page.pdfAttached File17.46 kBAdobe PDFView/Open
02_certificate.pdf1.21 MBAdobe PDFView/Open
03_abstract.pdf207.1 kBAdobe PDFView/Open
04_acknowledgement.pdf80.59 kBAdobe PDFView/Open
05_table of content.pdf416.58 kBAdobe PDFView/Open
06_list of table.pdf128.23 kBAdobe PDFView/Open
07_list of figures.pdf256.27 kBAdobe PDFView/Open
08_list of symbol and abbreviations.pdf128.91 kBAdobe PDFView/Open
09_chapter 1.pdf1.93 MBAdobe PDFView/Open
10_chapter 2.pdf1.2 MBAdobe PDFView/Open
11_chapter 3.pdf457.61 kBAdobe PDFView/Open
12_chapter 4.pdf330.71 kBAdobe PDFView/Open
13_chapter 5.pdf1.25 MBAdobe PDFView/Open
14_chapter 6.pdf332.57 kBAdobe PDFView/Open
15_references.pdf976.44 kBAdobe PDFView/Open
16_list of publication.pdf157.14 kBAdobe PDFView/Open
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