1. Shodhganga@INFLIBNET
  2. Anna University
  3. Faculty of Information and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/233470
Title: Design of compact floating point architecture with faster processing elements
Researcher: M, Kiruba
Guide(s): Sumathy, V
Keywords: Add-Shift
DiscreteWavelet
FloatingPoint
Multiplier
ResourceConsumption
University: Anna University
Completed Date: 2018
Abstract: Abstract available
Pagination: xxiii, 187p.
URI: http://hdl.handle.net/10603/233470
Appears in Departments:Faculty of Information and Communication Engineering

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01_title page.pdfAttached File8.99 kBAdobe PDFView/Open
02_certificate.pdf450.58 kBAdobe PDFView/Open
03_abstract.pdf391.3 kBAdobe PDFView/Open
04_acknowledgement.pdf81.89 kBAdobe PDFView/Open
05_table of content.pdf320.02 kBAdobe PDFView/Open
06_list of table.pdf232.07 kBAdobe PDFView/Open
07_list of figures.pdf242.58 kBAdobe PDFView/Open
08_list of symbol and abbreviations.pdf412.87 kBAdobe PDFView/Open
09_chapter 1.pdf1.47 MBAdobe PDFView/Open
10_chapter 2.pdf353.36 kBAdobe PDFView/Open
11_chapter 3.pdf834.13 kBAdobe PDFView/Open
12_chapter 4.pdf801.94 kBAdobe PDFView/Open
13_chapter 5.pdf1.64 MBAdobe PDFView/Open
14_chapter 6.pdf427.25 kBAdobe PDFView/Open
15_references.pdf676.25 kBAdobe PDFView/Open
16_list of publication.pdf71.82 kBAdobe PDFView/Open
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