1. Shodhganga@INFLIBNET
  2. Anna University
  3. Faculty of Information and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/232976
Title: Design and implementation of VLSI architecture for image scaling using space variant edge detection and bilinear interpolation
Researcher: N, Murali
Guide(s): Arokiasamy, A
Keywords: Bilinear
Detection
Digital
Image
VLSI
University: Anna University
Completed Date: 2017
Abstract: Abstract available
Pagination: xiv, 122p.
URI: http://hdl.handle.net/10603/232976
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File29.9 kBAdobe PDFView/Open
02_certificate.pdf531.66 kBAdobe PDFView/Open
03_abstract.pdf7.33 kBAdobe PDFView/Open
04_acknowledgement.pdf4.5 kBAdobe PDFView/Open
05_table of content.pdf11.43 kBAdobe PDFView/Open
06_list of table.pdf3.4 kBAdobe PDFView/Open
07_list of figures.pdf6.58 kBAdobe PDFView/Open
08_list of abbreviation.pdf3.8 kBAdobe PDFView/Open
09_chapter 1.pdf316.63 kBAdobe PDFView/Open
10_chapter 2.pdf540.75 kBAdobe PDFView/Open
11_chapter 3.pdf168.14 kBAdobe PDFView/Open
12_chapter 4.pdf431.9 kBAdobe PDFView/Open
13_chapter 5.pdf759.15 kBAdobe PDFView/Open
14_chapter 6.pdf59.57 kBAdobe PDFView/Open
15_appendix 1.pdf104.91 kBAdobe PDFView/Open
16_references.pdf129.29 kBAdobe PDFView/Open
17_list of publication.pdf14.12 kBAdobe PDFView/Open
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