Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/232956
Title: Performance evaluation of energy efficient adders in programmable truncated multiply and accumulate architectures
Researcher: E, John Alex
Guide(s): M, Vijayaraj
Keywords: AccumulatorCircuit
Architectures
DynamicPower
SignalProcessors
SleepMode
University: Anna University
Completed Date: 2018
Abstract: Abstract available
Pagination: xxv, 161p.
URI: http://hdl.handle.net/10603/232956
Appears in Departments:Faculty of Information and Communication Engineering

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01_title page.pdfAttached File24.97 kBAdobe PDFView/Open
02_certificate.pdf434.58 kBAdobe PDFView/Open
03_abstract.pdf18.69 kBAdobe PDFView/Open
04_acknowledgement.pdf5.11 kBAdobe PDFView/Open
05_table of content.pdf26.64 kBAdobe PDFView/Open
06_list of table.pdf9.18 kBAdobe PDFView/Open
07_list of figures.pdf183.05 kBAdobe PDFView/Open
08_list of symbol and abbreviations.pdf93.49 kBAdobe PDFView/Open
09_chapter 1.pdf691.39 kBAdobe PDFView/Open
10_chapter 2.pdf824.46 kBAdobe PDFView/Open
11_chapter 3.pdf837.37 kBAdobe PDFView/Open
12_chapter 4.pdf793.86 kBAdobe PDFView/Open
13_chapter 5.pdf1.58 MBAdobe PDFView/Open
14_chapter 6.pdf121.58 kBAdobe PDFView/Open
15_chapter 7.pdf19.11 kBAdobe PDFView/Open
16_references.pdf899.72 kBAdobe PDFView/Open
17_list of publication.pdf90.47 kBAdobe PDFView/Open
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