Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/232800
Title: Investigations on area efficient floating point arithmetic architectures
Researcher: K, Thiruvenkadam
Guide(s): Ramesh, J
Keywords: DSP
Dynamicrange
Floatingpointarithmetic
Highperformance
VLSI
University: Anna University
Completed Date: 2018
Abstract: Abstract available
Pagination: xxii, 119p.
URI: http://hdl.handle.net/10603/232800
Appears in Departments:Faculty of Information and Communication Engineering

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01_title page.pdfAttached File93.16 kBAdobe PDFView/Open
02_certificate.pdf1.09 MBAdobe PDFView/Open
03_abstract.pdf363.95 kBAdobe PDFView/Open
04_acknowledgement.pdf81.03 kBAdobe PDFView/Open
05_table of content.pdf481.99 kBAdobe PDFView/Open
06_list of table.pdf80.62 kBAdobe PDFView/Open
07_list of figures.pdf320.78 kBAdobe PDFView/Open
08_list of symbol and abbreviations.pdf239.39 kBAdobe PDFView/Open
09_chapter 1.pdf1.07 MBAdobe PDFView/Open
10_chapter 2.pdf1.55 MBAdobe PDFView/Open
11_chapter 3.pdf804.94 kBAdobe PDFView/Open
12_chapter 4.pdf645.26 kBAdobe PDFView/Open
13_chapter 5.pdf1.02 MBAdobe PDFView/Open
14_chapter 6.pdf357.57 kBAdobe PDFView/Open
15_references.pdf991.03 kBAdobe PDFView/Open
16_list of publication.pdf165.75 kBAdobe PDFView/Open
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