Design and implementation of efficient structures for digital interpolators

Abstract

To fulfill the ever increasing demand of modern electronic devices operating at the different sampling rates, the interest has touched its zenith in the up-sampling based discrete-time signal processing techniques, which can be incorporated by using the efficient digital interpolators. In this research work, the digital interpolators have been implemented efficiently and effectively using the field programmable gate arrays (FPGA) technology. It has also been demonstrated that how performance of the digital interpolators can be improved by using different techniques at the different sampling rates. First, the cascaded integrator comb (CIC) filters with compensation have been proposed using FPGA, and the results have been investigated for the different wireless standards. These results demonstrate that the logic utilization for global system for the mobile communication (GSM), wideband code division multiple access (WCDMA) and worldwide interoperability for the microwave access (WiMax) is 93%, 43% and 51% respectively. The worst case set up time for GSM, WCDMA and WiMax is 20.89 ns, 20.58 ns and 7.50 ns respectively. The worst case clock-to-output time for GSM, WCDMA and WiMax is 6.66 ns, 7.01 ns and 6.79 ns respectively. From the acquired results, it is evident that the CIC filters are efficient for the low-cost applications because the multipliers are not required in its implementation. Due to the absence of multipliers, they exhibit relatively fast response as compared to the conventional technology. However, the pass-band droop present in the CIC filters confine the scope of its practical applications. By employing compensation and multi-stage techniques, the response of CIC filter in the pass-band can be significantly improved, but at the cost of escalated hardware requirement and the computational complexity. For comparison purpose, the CIC filters have been implemented with and without compensation using the FPGA technology.