Certain investigations on reduced power consumption in sequential circuits

Abstract

The design automation of complex digital circuits in industry required reduced power consumption and increased throughput In today s industry the electronic equipment such as the microelectronic chip present in systems ranges variedly from cell phones to desktop computers to supercomputers which operate in basically the similar way A clock that is distributed globally synchronizes the operation of their millions of internal newlinecomponents Increasingly higher speed greater functionality and better energy efficiency chips can be achieved only by this global clocking which is now becoming a critical design challenge for the designers Asynchronous or clockless design is the apt alternative which precludes the need for global synchronization as a replacement operations of components are concurrent and synchronize locally based on necessity This destined work predominantly is dealt with the usage of asynchronous logic which is a novel approach in order to achieve low power design Mainly in the chosen Sequential circuits this work aims to make the design and performance analyses of circuits Both dual rail as well as single rail dynamic data paths are targeted in this design The new control structures and protocols are employed by the pipelines which aim at the reduction of handshaking delay which is the paramount impediment to achieve high throughput in asynchronous pipelines newline newline