Estimation of noise in high performance VLSI circuits

Abstract

Integrated circuit manufacturing industries are striving for cost effective, compact and handheld products in recent years. Therefore, the integration of digital circuits and analog/RF circuits over a common substrate is a viable solution. The system in which the digital and analog/RF block are sharing a common substrate, experiences an unwanted interaction amongst the various blocks. The switching activities in digital circuits inject noise in the substrate which is propagated through the common substrate to the sensitive analog circuits. This substrate noise coupling can therefore degrade the performance of the entire chip. Therefore, the accurate substrate modeling technique is a prime requirement for the analysis of substrate coupling in complex VLSI circuits. Existing substrate modeling techniques were either based on two dimensional simulations which are not sufficient since the substrate problem is inherently three dimensional, or required extraction of empirical parameters which make the models less predictable. In this thesis, a compact and more accurate substrate macromodel is proposed for the estimation of the substrate noise which encapsulates interactions amongst various types of circuits integrated on a System-on-Chip (SoC). This substrate macromodel is mainly dealing with resistive behavior of the substrate and by using the same resistive behavior of the substrate, the macromodel for the uniformly doped substrate as well as for multilayer substrate is developed to analyze the substrate noise coupling between the source and sensor circuits. These macromodels can further be used in complex VLSI circuits to estimate their performance in the presence of substrate noise coupling. The macromodel for the substrate is generics for all types of substrates, but the circuit macromodel is unique for every circuit. The variation in the performance of MOSFET devices in the presence of substrate coupling is presented to discerning the effect of substrate coupling in the MOSFET operation.