Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/229574
Title: Performance and reliability enhancement techniques for two dimensional network on chips using adaptive deflection routers
Researcher: Simi Zerine Sleeba
Guide(s): Mini M.G
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
Network on Chip
Permutation Deflection Network
University: Cochin University of Science and Technology
Completed Date: 2017
Abstract: newline
Pagination: 210 p
URI: http://hdl.handle.net/10603/229574
Appears in Departments:School of Engineering

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01_title.pdfAttached File5.73 kBAdobe PDFView/Open
02_declaration.pdf93.25 kBAdobe PDFView/Open
03_acknowledgements.pdf7.58 kBAdobe PDFView/Open
04_certificate.pdf29.87 kBAdobe PDFView/Open
05_abstract.pdf22.48 kBAdobe PDFView/Open
06_contents.pdf116.98 kBAdobe PDFView/Open
07_list of figures.pdf47.79 kBAdobe PDFView/Open
08_chapter 1.pdf238.83 kBAdobe PDFView/Open
09_chapter 2.pdf305.01 kBAdobe PDFView/Open
10_chapter 3.pdf1.37 MBAdobe PDFView/Open
11_chapter 4.pdf765.84 kBAdobe PDFView/Open
12_chapter 5.pdf1.97 MBAdobe PDFView/Open
13_chapter 6.pdf471.36 kBAdobe PDFView/Open
14_chapter 7.pdf31.82 kBAdobe PDFView/Open
15_references.pdf152.62 kBAdobe PDFView/Open
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