Investigation on mitigation of signal integrity issues in high speed digital circuits

Abstract

In recent years the development of the high speed digital design leads to smaller device or high density component packaging operation at high speed and very fewer voltage levels In mixed signal systems the RFIC s and the digital IC s are connected to the common substrate and are packed as SIP or SOP Inside the system millions of drivers and the receivers are connected by high speed interconnects. Interconnect carries signal with the rise time of few hundreds of pico second but the maximum frequency content of that signal is only a few tens of gigahertz At these frequencies interconnects can exhibit the transmission line behavior Especially during the simultaneous switching of the multiple drivers a high voltage drop occurs across interconnects which will propagate between the power ground plane pair Because of this power ground plane propagation the nearby RF Analog IC functionality performance are affected newlineTraditionally the power ground plane pair is considered as a parallel plate waveguide when the operating wavelength becomes a fraction of the PCB thickness This pair can support multiple resonances depending on its physical dimension If the nth harmonic of the generated noise is equal to any one of the power ground plane resonance then the noise will also propagate between the power ground plane pair This noise is called as simultaneous switching noise SSN or Ground Bounce Noise GBN It is considered as a major source of interference to the Analog RFICs in mixed signal systems Hence a proper isolation technique is necessary in order to isolate the RFIC from the noisy Digital IC in the context of the mixed signal system newlineIn the case of high density packaging the components and interconnects are very close to each other In high-speed digital circuits the increase in the operating frequency results in coupling of electromagnetic energy from one line to another It is called as a crosstalk newline newline