1. Shodhganga@INFLIBNET
  2. Vellore Institute of Technology, Vellore
  3. School of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/224384
Title: Analysis of Delay and Power dissipation in CNT based VLSI Interconnects
Researcher: Karthikeyan.A
Guide(s): Partha sharathi Mallick
Keywords: Engineering and Technology,Engineering,Engineering Electrical and Electronic
Power dissipation
VLSI Interconnects
University: VIT University
Completed Date: 2018
Abstract: newline
Pagination: I-XII,1-113
URI: http://hdl.handle.net/10603/224384
Appears in Departments:School of Electrical Engineering

Files in This Item:
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01_title.pdfAttached File99.23 kBAdobe PDFView/Open
02_certificate.pdf237.01 kBAdobe PDFView/Open
02_declaration.pdf252.31 kBAdobe PDFView/Open
03_abstract.pdf55.66 kBAdobe PDFView/Open
03__acknowledgement.pdf299.31 kBAdobe PDFView/Open
03_ list of figures.pdf109.35 kBAdobe PDFView/Open
03_ list of tables.pdf41.76 kBAdobe PDFView/Open
03_table of contents.pdf57.59 kBAdobe PDFView/Open
04_ chapter 1.pdf135.78 kBAdobe PDFView/Open
05_ chapter 2.pdf719.69 kBAdobe PDFView/Open
06_ chapter 3.pdf1.21 MBAdobe PDFView/Open
07_ chapter 4.pdf309.18 kBAdobe PDFView/Open
08_ chapter 5.pdf766.22 kBAdobe PDFView/Open
09_chapter 6.pdf1.32 MBAdobe PDFView/Open
10_references.pdf86.76 kBAdobe PDFView/Open
11_ list of publications.pdf0 BAdobe PDFView/Open
12_ list of publications.pdf39.27 kBAdobe PDFView/Open
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