Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/224124
Title: | Test Power Minimization Techniques for Digital VLSI Circuits |
Researcher: | Thilgavathi.K |
Guide(s): | Sivanantham.S |
Keywords: | Digital VLSI CIrcuits Engineering and Technology,Engineering,Engineering Electrical and Electronic |
University: | VIT University |
Completed Date: | 2018 |
Abstract: | newline |
Pagination: | I-XII, 1-115 |
URI: | http://hdl.handle.net/10603/224124 |
Appears in Departments: | School of Electronic Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 108.72 kB | Adobe PDF | View/Open |
02_certificate.pdf | 433.92 kB | Adobe PDF | View/Open | |
02_declaration.pdf | 488.57 kB | Adobe PDF | View/Open | |
03_abstract.pdf | 60.85 kB | Adobe PDF | View/Open | |
03_preliminary pages.pdf | 290.5 kB | Adobe PDF | View/Open | |
04_chapter 1.pdf | 284.93 kB | Adobe PDF | View/Open | |
05_chapter 2.pdf | 450.37 kB | Adobe PDF | View/Open | |
06_chapter 3.pdf | 443.82 kB | Adobe PDF | View/Open | |
07_chapter 4.pdf | 228.83 kB | Adobe PDF | View/Open | |
08_chapter 5.pdf | 341.82 kB | Adobe PDF | View/Open | |
09_chapter 6.pdf | 232.26 kB | Adobe PDF | View/Open | |
10_conclusion.pdf | 47.73 kB | Adobe PDF | View/Open | |
11_references.pdf | 101.24 kB | Adobe PDF | View/Open | |
12_publications.pdf | 42.95 kB | Adobe PDF | View/Open |
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