Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/224124
Title: Test Power Minimization Techniques for Digital VLSI Circuits
Researcher: Thilgavathi.K
Guide(s): Sivanantham.S
Keywords: Digital VLSI CIrcuits
Engineering and Technology,Engineering,Engineering Electrical and Electronic
University: VIT University
Completed Date: 2018
Abstract: newline
Pagination: I-XII, 1-115
URI: http://hdl.handle.net/10603/224124
Appears in Departments:School of Electronic Engineering

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01_title.pdfAttached File108.72 kBAdobe PDFView/Open
02_certificate.pdf433.92 kBAdobe PDFView/Open
02_declaration.pdf488.57 kBAdobe PDFView/Open
03_abstract.pdf60.85 kBAdobe PDFView/Open
03_preliminary pages.pdf290.5 kBAdobe PDFView/Open
04_chapter 1.pdf284.93 kBAdobe PDFView/Open
05_chapter 2.pdf450.37 kBAdobe PDFView/Open
06_chapter 3.pdf443.82 kBAdobe PDFView/Open
07_chapter 4.pdf228.83 kBAdobe PDFView/Open
08_chapter 5.pdf341.82 kBAdobe PDFView/Open
09_chapter 6.pdf232.26 kBAdobe PDFView/Open
10_conclusion.pdf47.73 kBAdobe PDFView/Open
11_references.pdf101.24 kBAdobe PDFView/Open
12_publications.pdf42.95 kBAdobe PDFView/Open
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