Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/22180
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.coverage.spatial | Physics | en_US |
dc.date.accessioned | 2014-08-05T10:36:01Z | - |
dc.date.available | 2014-08-05T10:36:01Z | - |
dc.date.issued | 2014-08-05 | - |
dc.identifier.uri | http://hdl.handle.net/10603/22180 | - |
dc.description.abstract | None | en_US |
dc.format.extent | - | en_US |
dc.language | English | en_US |
dc.relation | - | en_US |
dc.rights | university | en_US |
dc.title | Studies on jitter response and design dependent dynamics of some Pll based clock or data recovery circuits | en_US |
dc.title.alternative | - | en_US |
dc.creator.researcher | Ghosh, Madhusudan | en_US |
dc.subject.keyword | Physics | en_US |
dc.description.note | - | en_US |
dc.contributor.guide | Sarkar, Bishnu Charan | en_US |
dc.publisher.place | Bardhaman | en_US |
dc.publisher.university | The University of Burdwan | en_US |
dc.publisher.institution | Department of Physics | en_US |
dc.date.registered | 20-9-2000 | en_US |
dc.date.completed | n.d. | en_US |
dc.date.awarded | 14/05/2013 | en_US |
dc.format.dimensions | - | en_US |
dc.format.accompanyingmaterial | None | en_US |
dc.source.university | University | en_US |
dc.type.degree | Ph.D. | en_US |
Appears in Departments: | Department of Physics |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
dissertation submitted by madhusudan ghosh.pdf | Attached File | 2.75 MB | Adobe PDF | View/Open |
synopsis submitted by madhusudan ghosh.pdf | 108.77 kB | Adobe PDF | View/Open |
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