Design and Analysis of High Performance Charge Pump for Digital Phase Locked Loops

Abstract

In many applications especially wireless communication, commonly digital phase locked loop is used for frequency synthesis. It can be implemented in two architectures; they are integer-N PLL and fractional PLL. In this thesis integer-N charge pump PLL is chosen because of its tremendous advantages. Integer-N charge pump involves blocks, namely, Phase Frequency Detector, Charge pump, Loop Filter, Voltage Controlled Oscillator and Divider. Modeling exhibits variations of charge pump current results loop stability issues. Phase error by phase frequency detector generates proportional output voltage by charge pump, which is filtered and processed through voltage controlled oscillator. Till the loop locks, iteration continues to generate variable charge pump out voltage to vary the output of voltage controlled oscillator. It states charge pump converts phase error into voltage, thus it is very prominent in loop. newlineThis thesis gives brief overview of charge pump PLL and reports in-depth analysis of the design and working of a charge pump for charge pump PLL in 65nm CMOS technology. Prominent of Charge pump and its design challenges are discussed. Overview of single ended charge pump and fully differential charge pump is discussed. In this research work, three types of charge pump are proposed and are verified their functionality in DPLL for speed of 1GHz using tsmc 65nm CMOS technology. newline