A Narrow band Band pass ADC for IF Receivers

Abstract

A new fS/4 bandpass (Delta-Sigma)-ADC (Analog-to-Digital Conveter) architecture is realized by feeding back the delayed quantization noise nherently produced by a pipelined ADC. Designed in 55-nm Global Foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves SNDR of 72 dB, 75.8 dB, 80.1 dB, and 85.3 dB in 15.64 MHz,7.82 MHz, 3.91 MHz, and 1.953 MHz band, respectively around a center frequency of 62.5MHz with only 1st-order noise shaping, while consuming 103 mW of power, and achieving a maximum FoM of 158 dB. The work also proposes a dithering based calibration technique which facilitates accurate estimation of the interstage gain and capacitor mismatch errors in pipelined ADC stages with minimal hardware overhead, thus realizing pipelined ADCs achieving the theoretical maximum SFDR. The proposed technique is validated both at system level using MATLAB and then at circuit level in Cadence. The proposed calibration method is consequently used in the proposed band-pass modulator to achieve an ADC with linearity in excess of 100 dB.As the last phase of the work, a wide-band tunable, band-pass ADC for multi channel receivers, is proposed. The tunability is realized by modifying the proposed pipelined ADC based band-pass ADC architecture. A switch capacitor based error-delaying circuitry is used to delay the quantization error generated by a pipelined ADC in variable number of cycles to realize a continuum of notches in the Noise Transfer Function (NTF) of the ADC. A prototype is designed in 55nm Global Foundry (GF) CMOS process and simulation results are reported. The simulated prototype runs at 500 MHz, achieves Signal-To-Noise Ratio (SNR) in excess of 80 dB, and tunable to quantize signals from 34 MHz to 885 MHz.