1. Shodhganga@INFLIBNET
  2. SASTRA University
  3. School of Computing
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/217884
Title: Performance Enhanced Architectures and Organizations of Bufferless Network on Chip
Researcher: Muralidharan, D
Guide(s): Muthaiah, R
Keywords: Chipper
Network- On- Chip NOC
University: SASTRA University
Completed Date: 2018
Abstract: Abstract included newline
Pagination: xii, 113p
URI: http://hdl.handle.net/10603/217884
Appears in Departments:School of Computing

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01_title_page.pdfAttached File6.74 kBAdobe PDFView/Open
02_dedication.pdf34.54 kBAdobe PDFView/Open
03_acknowledgment.pdf39.26 kBAdobe PDFView/Open
04_table_of_contents.pdf38.72 kBAdobe PDFView/Open
05_list_of_tables.pdf34.76 kBAdobe PDFView/Open
06_list_of_figures.pdf36.86 kBAdobe PDFView/Open
07_abstract.pdf41.93 kBAdobe PDFView/Open
08_chapter_01.pdf95.02 kBAdobe PDFView/Open
09_chapter_02.pdf141.11 kBAdobe PDFView/Open
10_chapter_03.pdf220.91 kBAdobe PDFView/Open
11_chapter_04.pdf668.22 kBAdobe PDFView/Open
12_chapter_05.pdf119.32 kBAdobe PDFView/Open
13_chapter_06.pdf125.06 kBAdobe PDFView/Open
14_chapter_07.pdf26.58 kBAdobe PDFView/Open
15_references.pdf60.65 kBAdobe PDFView/Open
16_list_of_abbreviations.pdf19.41 kBAdobe PDFView/Open
17_list_of_publications.pdf22.56 kBAdobe PDFView/Open
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