1. Shodhganga@INFLIBNET
  2. Pondicherry University
  3. Department of Computer Science
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/217714
Title: Design of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique
Researcher: Uma, R.
Guide(s): Dhavachelvan, P.
Keywords: low power
high speed
gate diffusion
input technique
accumulate unit
University: Pondicherry University
Completed Date: 2015
Abstract: newline
Pagination: xviii, 246 p.
URI: http://hdl.handle.net/10603/217714
Appears in Departments:Department of Computer Science

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01_title.pdfAttached File220.27 kBAdobe PDFView/Open
02_certificate.pdf100.02 kBAdobe PDFView/Open
03_abstract.pdf9.15 kBAdobe PDFView/Open
04_acknowledgement.pdf84.92 kBAdobe PDFView/Open
05_table of contents.pdf173.24 kBAdobe PDFView/Open
06_abbrevations.pdf14.3 kBAdobe PDFView/Open
07_list of tables.pdf11.44 kBAdobe PDFView/Open
08_list of figures.pdf113.44 kBAdobe PDFView/Open
09_chapter 1.pdf171.14 kBAdobe PDFView/Open
10_chapter 2.pdf566.3 kBAdobe PDFView/Open
11_chapter 3.pdf697.9 kBAdobe PDFView/Open
12_chapter 4.pdf1.25 MBAdobe PDFView/Open
13_chapter 5.pdf660.94 kBAdobe PDFView/Open
14_chapter 6.pdf1.05 MBAdobe PDFView/Open
15_chapter 7.pdf1.23 MBAdobe PDFView/Open
16_chapter 8.pdf166.68 kBAdobe PDFView/Open
17_references.pdf262.92 kBAdobe PDFView/Open
18_publications.pdf231.94 kBAdobe PDFView/Open
19_appendix.pdf130.06 kBAdobe PDFView/Open
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