Design and Implementation of Quantum dot Cellular Automata QCA Based Novel Logic Circuits

Abstract

The work carried out in this thesis is concerned with the design of electronic logic circuits using Quantum-dot Cellular Automata (QCA). The thesis presents detailed theory about QCA technology and terminology. Several initial designs and newlineimplementations, available in literature, have been discussed for an in-depth understanding of the subject. It has been observed that here is a scope for designing and implementing new QCA-based logic circuits and applications with improved circuit parameters like area, circuit complexity and clock delays. This forms motivation to conduct the work carried out under this research programme. It also presents in-depth study of QCA circuits and summarizes various contemporary literatures available in this direction. The significance of conducting research on the topic of this thesis has newlinebeen amply justified. newlineCombinational approach to implement QCA based logic circuits has been discussed. An attempt has been made to implement QCA based XOR and XNOR gates with improved circuit parameters. Typical circuit parameters like design complexity, speed and power consumption has been considered while proposing new QCA based circuits in this thesis. Combinational logic circuits like Inverter/Buffer have been implemented using the proposed QCA based XOR/XNOR gates. newlineNovel Code-Converter circuits using the proposed QCA XOR gate have been implemented. Typically, N-bit Binary-to-Gray code converter and 4-bit Excess-3 code converter circuits have been proposed using QCA. The proposed Code-Converters have been tested for their comparative advantages using computer simulation tests. newlineA new multi-functional logic gate entitled Modified-Majority Voter (M-MV) has been implemented and presented in the thesis. The proposed circuit has been tested for genunity of its design Several logic circuits including basic gates like AND/OR/XOR/XNOR gates and other combinational logic circuits such as Full newlineAdder/Subtractor circuits and Parity generator/Checker circuits have been implemented using the proposed M-MV...