1. Shodhganga@INFLIBNET
  2. Jaypee Institute of Information Technology
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/215286
Title: ANALYSIS OF POWER REDUCTION TECHNIQUES AND LOW POWER ESTIMATION MODEL FOR FPGA IMPLEMENTATIONS
Researcher: Verma, Gaurav
Guide(s): Khare, Vijay
Keywords: circuit phase
Clock Gating with One Hot Enabling
embedded multiplier
Field Programmable
wearable devices
University: Jaypee Institute of Information Technology
Completed Date: 27/08/2018
Abstract: included newline
URI: http://hdl.handle.net/10603/215286
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File106.75 kBAdobe PDFView/Open
02_table of contents.pdf201.02 kBAdobe PDFView/Open
03_declaration.pdf224.69 kBAdobe PDFView/Open
04_certificate.pdf224.84 kBAdobe PDFView/Open
05_ackowledgement.pdf87.96 kBAdobe PDFView/Open
06_abstract.pdf90.02 kBAdobe PDFView/Open
07_list of acronyms and abbreviations.pdf89.84 kBAdobe PDFView/Open
08_list of figures and tables.pdf172.22 kBAdobe PDFView/Open
09_chapter1.pdf603.62 kBAdobe PDFView/Open
10_chapter2.pdf775.4 kBAdobe PDFView/Open
11_chapter3.pdf619.6 kBAdobe PDFView/Open
12_chapter4.pdf435.24 kBAdobe PDFView/Open
13_chapter5.pdf178.43 kBAdobe PDFView/Open
14_appendix.pdf350.76 kBAdobe PDFView/Open
15_references.pdf262.83 kBAdobe PDFView/Open
16_list of publication.pdf208.68 kBAdobe PDFView/Open
17_synopsis.pdf180.4 kBAdobe PDFView/Open
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