1. Shodhganga@INFLIBNET
  2. University of Mysore
  3. Department of Electronics
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/204394
Title: Bist based low transition test pattern generation for minimizing test power in VLSI circuits
Researcher: Praveen, J.
Guide(s): Shanmukha Swamy, M. N.
Keywords: Linear Feedback Shift Register
Test Pattern Generator
VLSI Circuits
VLSI Testing
University: University of Mysore
Completed Date: 2016
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/204394
Appears in Departments:Department of Electronics

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File146.01 kBAdobe PDFView/Open
02_declaration.pdf7.72 kBAdobe PDFView/Open
03_certificate.pdf158.52 kBAdobe PDFView/Open
04_acknowledgement.pdf8.1 kBAdobe PDFView/Open
05_dedication.pdf83.63 kBAdobe PDFView/Open
06_abstarct.pdf174.98 kBAdobe PDFView/Open
07_contents.pdf157.81 kBAdobe PDFView/Open
08_list of tables.pdf20.69 kBAdobe PDFView/Open
09_list of figures.pdf98.13 kBAdobe PDFView/Open
10_abbreviation.pdf87.97 kBAdobe PDFView/Open
11_chapter 1.pdf355.33 kBAdobe PDFView/Open
12_chapter 2.pdf221 kBAdobe PDFView/Open
13_chapter 3.pdf1.34 MBAdobe PDFView/Open
14_chapter 4.pdf1.09 MBAdobe PDFView/Open
15_chapter 5.pdf2.79 MBAdobe PDFView/Open
16_chapter 6.pdf2.36 MBAdobe PDFView/Open
17_chapter 7.pdf188.82 kBAdobe PDFView/Open
18_list of publications.pdf166.5 kBAdobe PDFView/Open
19_references.pdf292.04 kBAdobe PDFView/Open
20_appendix.pdf1.24 MBAdobe PDFView/Open
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