Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/204017
Title: Optimized complex multiplier and modified bit parallel multiplier based radix 2 and radix 4 pipelined fft architecture
Researcher: Rao, Hanumantha K
Guide(s): Paul, Charlie Kumar C
Keywords: Algorithms
Digital signal processing
University: St. Peters University
Completed Date: 2016
Abstract: None
Pagination: 154 p.
URI: http://hdl.handle.net/10603/204017
Appears in Departments:Department of Electronics and Communication

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01_title.pdfAttached File227.17 kBAdobe PDFView/Open
02_certificate.pdf196.12 kBAdobe PDFView/Open
03_declaration.pdf135.55 kBAdobe PDFView/Open
04_acknowledgements.pdf144.52 kBAdobe PDFView/Open
05_abstract.pdf89.75 kBAdobe PDFView/Open
06_content.pdf94.59 kBAdobe PDFView/Open
07_list of tables and figures.pdf177.22 kBAdobe PDFView/Open
08_abbreviations.pdf91.39 kBAdobe PDFView/Open
09_chapter 1.pdf611.24 kBAdobe PDFView/Open
10_chapter 2.pdf319.66 kBAdobe PDFView/Open
11_chapter 3.pdf2.18 MBAdobe PDFView/Open
12_chapter 4.pdf7.37 MBAdobe PDFView/Open
13_chapter 5.pdf1.23 MBAdobe PDFView/Open
14_chapter 6.pdf291.02 kBAdobe PDFView/Open
15_chapter 7.pdf90.29 kBAdobe PDFView/Open
16_references.pdf326 kBAdobe PDFView/Open
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