Design and Implementation of efficient Artificial Neural Network architecture for embedded application

Abstract

Low power gate level data path optimizations are presented for Artificial Neural Network (ANN) architecture to address the low power ANN applications in the field of science and engineering. Efficient 4:2 compressor architecture is proposed for the multiplier architecture of ANN layered structure. Proposed data path architectural optimizations are illustrated in the 2-3-1 three layer artificial neural network (ANN). Verilog HDL was used to model the design in ASIC domain with 65nm technological CMOS library. The proposed concept has resulted with 12.71 % better speed, 15.94 % less area and 26.09 % less leakage power consumption. newline