Vtmos-a new logic family for low power digital circuits

Abstract

The need for extending low power circuits increased with the advent of use of large number of portable devices like cell phones, calculators , miniature computers etc. In all these devices one of the burning problems is increasing the life of battery .This can be achieved by reducing the power consumption of the individual circuits .One of the methods of reducing the power consumption is by operating the devices at low currents and low voltages. It is known that MOS devices and circuits, especially CMOS circuits newlineconsume relatively low power .But there seems to be a need to reduce this power further to prolong the life of the battery. MOSFET devices are generally operated above threshold voltages. But the devices can also newlineexhibit control characteristics, even below the threshold voltages .This region of operation of these devices may be called as sub threshold operation. Basically, the principle of sub threshold logic is, operating MOSFET in sub threshold region and using the leakage current in that newlineregion for switching action, there by significantly decreasing the power newlineconsumption. The sub threshold circuits experience large delays and hence they cannot be used in high frequency applications .Several approaches have been made for improving the speed of the devices. newlineDynamic Threshold MOSFET (DTMOS) technique is one such technique where body is connected to gate. This technique provides high current newlinedrive compared to CMOS circuits operated at lower voltages (i.e at sub threshold voltages).The leakage current produced by DTMOS circuits ii during OFF state is comparable with leakage currents of CMOS circuits. To reduce the leakage currents and power dissipation of DTMOS circuits, further a new technique called Variable Threshold MOSFET (VTMOS) technique is proposed in the thesis. newline