Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/195787
Title: Design and FPGA implementation of a novel reconfigurable adaptive router for network on chip
Researcher: G, Selvaraj
Guide(s): Kashwan, K R
Keywords: Algorithms
Arbitration
Buffering
Switches
Switching
University: Anna University
Completed Date: 2016
Abstract: Abstract available
Pagination: xxi, 119p.
URI: http://hdl.handle.net/10603/195787
Appears in Departments:Faculty of Information and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File23.56 kBAdobe PDFView/Open
02_certificate.pdf1.13 MBAdobe PDFView/Open
03_abstract.pdf16.31 kBAdobe PDFView/Open
04_acknowledgement.pdf4.64 kBAdobe PDFView/Open
05_table of content.pdf23.16 kBAdobe PDFView/Open
06_list of table.pdf9.21 kBAdobe PDFView/Open
07_list of figures.pdf18.49 kBAdobe PDFView/Open
08_list of symbol and abbreviations.pdf22.31 kBAdobe PDFView/Open
09_chapter 1.pdf185.69 kBAdobe PDFView/Open
10_chapter 2.pdf140.44 kBAdobe PDFView/Open
11_chapter 3.pdf840.55 kBAdobe PDFView/Open
12_chapter 4.pdf619.64 kBAdobe PDFView/Open
13_chapter 5.pdf24.78 kBAdobe PDFView/Open
14_chapter 6.pdf15.79 kBAdobe PDFView/Open
15_references.pdf76.98 kBAdobe PDFView/Open
16_list of publication.pdf8.84 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: