Memory customization in multiprocessor Systems-On-Chip

Abstract

With the change in time, there is increase in the demand of embedded system applications with advanced technologies. Multiprocessor Systems-on-Chip (MPSoC s) become usual in embedded systems to provide required power efficient systems. The power consumed and performance of the system majorly depends on the memory organization of the system and hence requiring system with low power memory organizations. The aim of this dissertation is to find solutions of various issues involved in cache memory design with respect to shared and private memory systems being used by multiple processors. newlineThe first issue is multiple processor synchronization. This problem generally occurs in case of shared memory. A semaphore solution with the intent of decreasing energy consumption and cache miss rate is proposed to solve the problem of synchronization among processors in shared memory architecture. The second issue is the use of replacement policies in SPM. The use of Scratch pad memory with three different replacement policies FIFO, LRU and Random have been proposed which has been never done earlier. newlineThe third major problem is the need of a simulator which provides the shared memory environment for multiprocessors. So, in this thesis, a Memory Map simulator having multiprocessors with shared memory architecture is designed. Memory Map is a simulator which can simulate system having multiple processors with shared and private caches configuration. The metrics cache miss rate and cache hit rate can be evaluated using this simulator. In this simulator, user can reconfigure cache memory and can also alter the number of processors within the application program.